A Parametrizable Processor

System-on-a-chip solutions often require simple processors designed to perform a narrow variety of tasks meeting certain performance specifications. It is important to use processors that perform the required tasks with minimal waste of chip area and power consumption, however there are engineering expenses to design an optimal processor for each SOC solution. Starting from a 3-stage pipelined SMIPS processor in Bluespec, we designed and implemented a parametrizable processor, which can be configured at compile-time to be synthesized as a one, two or three-stage processor. According to the parameter choice, the processor is synthesized only with the hardware required to run the specified pipeline configuration. Our results indicate that low-stage solutions have lower IPS performance and lower area, and the performance / area tradeoff is balanced throughout all possible processor configurations.